1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Background Art
An example of a nonvolatile memory includes an EPROM (Erasable and Programmable Read Only Memory) which is a ROM capable of electrically rewriting data. An EPROM is generally classified into a UV-EPROM using ultraviolet rays for data erase and an EEPROM (Electrical Erasable and Programmable Read Only Memory) electrically erasing data. An EEPROM does not erase data partially, but erases all pieces of data and, then, writes data to each memory cell.
An EEPROM can be mounted to a microcomputer for a mobile telephone, a digital home appliance or the like. For example, it is possible to form a semiconductor integrated circuit in which such an EEPROM and a CPU (Central Processing Unit) are formed on a surface of a chip.
An EEPROM includes an ONO (Oxide Nitride Oxide) film serving as a charge accumulation film for accumulating electrical charge in some cases. An EEPROM has, for example, a MONOS (Metal Oxide Nitride Oxide Semiconductor) structure using an ONO film or a SONOS (Silicon Oxide Nitride Oxide Semiconductor) structure. For example, data is written to such a nonvolatile memory when electrons are injected into an ONO film. In addition, data is erased from the nonvolatile memory when holes are injected into the ONO film and, then, are recombined with the accumulated electrons.
Japanese Patent Laying-Open No. 2003-309193 discloses a memory cell transistor having the following structure. That is, a pair of memory electrodes one of which is set at a source electrode and the other one of which is set at a drain electrode mutually and a channel region interposed between the pair of memory electrodes are formed on a first well region. Further, a first gate electrode is provided near the memory electrode on the channel region with an insulating film interposed between the first gate electrode and the channel region. A second gate electrode is also provided on the channel region with an insulating film and a charge accumulation region each interposed between the second gate electrode and the channel region, and is electrically isolated from the first gate electrode.
Japanese Patent Laying-Open No. 2003-100916 discloses a MONOS-type nonvolatile memory device in which a word gate, an impurity layer and sidewall-shaped first and second control gates are formed on a first gate insulating film formed on a semiconductor substrate. Herein, each of the first and second control gates has a rectangular sectional shape.
In Byung Yong Choi, et al., “Highly Scalable and Reliable 2-bit/cell SONOS Memory Transistor beyond 50 nm NVM Technology Using Outer Sidewall Spacer Scheme with Damascene Gate Process”, IEEE 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 118-119, there is described a two-bit/cell SONOS memory transistor beyond 50 nm NVM technology. In a method for manufacturing such a memory transistor, first, an ONO film is formed on a surface of a semiconductor substrate. Then, in the ONO film, a portion corresponding to a substantially center of a channel is removed; thus, two separated storage nodes are formed. This memory exhibits high reliability even when being finely manufactured so as to have a gate length of 80 nm.
Japanese Patent Laying-Open No. 2004-111629 discloses a manufacturing method of a MONOS memory. This manufacturing method includes: forming a first gate insulating layer above a semiconductor substrate; forming a first conductive layer word gate and a stopper layer; forming a first insulating layer and a second insulating layer on an entire memory region; performing anisotropic etching on the second insulating layer, thereby forming a first sidewall conductive layer; forming a third conductive layer on the entire memory region; performing anisotropic etching on the third conductive layer, thereby forming a second sidewall conductive layer; and performing isotropic etching on the first and second sidewall conductive layers, thereby forming a control gate.
Japanese Patent Laying-Open No. 11-145471 discloses a semiconductor device in which an element isolation region is formed on a semiconductor substrate and a gate electrode is formed on the semiconductor substrate with a gate insulating film interposed between the gate electrode and the semiconductor substrate. Herein, an insulating film having a thickness “a” is formed on a top face of the gate electrode, and a sidewall having a thickness “b” at a lowermost side is formed on a side face of the gate electrode. The thickness of the sidewall at the height of “a” from the top face of the gate electrode is not less than “b”, wherein “a”≧“b”.
A memory having a MONOS structure of a split gate type includes a control gate electrode of a control transistor and a memory gate electrode of a MONOS transistor. The memory gate electrode is provided beside the control gate electrode with an insulating film interposed between the memory gate electrode and the control gate electrode. An ONO film serving as a charge accumulation film is formed between the memory gate electrode and a semiconductor substrate.
In the memory having the MONOS structure of the split gate type, the memory gate electrode is formed as a sidewall of the control gate electrode. More specifically, the control gate electrode is formed by photolithography through a mask. On the other hand, the memory gate electrode is formed by etching in a self aligned manner. The memory gate electrode has an inclined top face in a sectional shape thereof. In other words, the top face gradually becomes low in height toward an outer side. The memory gate electrode is high in height on a side near the control gate electrode and gradually becomes low in height toward an outer side.
In a step of forming a diffusion layer such as a source region or a drain region on a semiconductor substrate, ion implantation is performed in a self aligned manner while using the control gate electrode or the memory gate electrode as a mask. Since the outer side of the memory gate electrode is low in height, ions implanted upon performance of the ion implantation transmit through the memory gate electrode and, then, reach the charge accumulation film in some cases. Consequently, there arises a problem that the ONO film serving as the charge accumulation film is degraded.
There is a design rule as a parameter indicating a level of microfabrication. In a case that a manufacturable minimum dimension is set as such a design rule, recently, a semiconductor device is manufactured below a 90 nm rule. In a photolithography step upon manufacturing of a fine semiconductor device, an ArF light source is used as a light source for exposure, in place of a conventional KrF light source. If the ArF light source is used, a fine circuit can be formed. However, it is necessary to make a portion to be exposed, such as a resist, thin. If the resist is thin, a depth capable of performing etching becomes shallow in an etching step after development of the resist.
In a semiconductor device, for example, an interlayer insulating film is formed on a top face of a memory cell. The interlayer insulating film is formed for planarizing a surface and is provided on the top face of the memory cell. An interconnection is provided on the surface of the interlayer insulating film, for example. In order to electrically connect between the interconnection and the memory cell, a contact is formed so as to pass through the interlayer insulating film. Upon formation of the contact, a through hole, which has a length equal to a sum of a height of the memory cell and a height from a top of the memory cell to the surface of the interlayer insulating film, must be formed in the interlayer insulating film.
In the semiconductor device in accordance with the design rule below a 90 nm rule, however, the ArF light source is used for exposure. Therefore, there arises a problem that the resist becomes thin in thickness, so that a contact hole passing through the interlayer insulating film cannot be formed in a step of forming a contact hole. To this end, there is required that a thickness of an interlayer insulating film is made thin in a semiconductor device including a memory cell.
In order to prevent that ions are implanted into a charge accumulation film, it is considered that a height of a memory gate electrode is made high. However, if the height of the memory gate electrode is high, there arises a problem that a thickness of an interlayer insulating film becomes large. Alternatively, in order to prevent that ions are implanted into a charge accumulation film, it is considered that energy of ions to be implanted is made small in an ion implantation step. However, the energy of the ions to be implanted is determined based on necessity of countermeasures against short circuit failure between a diffusion layer and a substrate upon silicidation. Consequently, there arises a problem that it is impossible to make the energy of the ions to be implanted small.
As a semiconductor circuit is formed finely, a gate electrode formed on an insulating film formed on a surface of a semiconductor substrate must be decreased in dimension. Consequently, there arises a problem that dimensional accuracy becomes poor when the dimension of the gate electrode is made small.